发明名称 Input circuit
摘要 An input circuit according to the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means, and enhancing the latching operation of the data latch means.
申请公布号 US2004090251(A1) 申请公布日期 2004.05.13
申请号 US20030697267 申请日期 2003.10.31
申请人 NEC ELECTRONICS CORPORATION 发明人 WATARAI SEIICHI
分类号 H03K19/096;H03K3/012;H03K3/356;H03K19/0175;(IPC1-7):H03L7/00 主分类号 H03K19/096
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