| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce a hardware amount of a clock transfer circuit without setting phases of a writing clock and a reading clock. <P>SOLUTION: A low-order writing address 13 and a high-order writing address 14 are sent by a writing frame pulse signal 11 and a writing clock signal 12 so as to write input data 10 into a 2-port RAM 1. The RAM 1 secures an address area of n fames. A reading control unit 4 generates a high-order reading address 24, based on a reading control signal 30 and the high-order writing address 14. A low-order reading address 23 and the high-order reading address 24 from the reading control unit 4 are sent by a reading frame pulse signal 21 and a reading clock signal 22 as output data 20 from the RAM 1. Since reading areas are generated so as not to overlap by determining writing areas, an interval between writing and reading can be fully held. <P>COPYRIGHT: (C)2004,JPO</p> |
