发明名称 |
Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset method |
摘要 |
Provided are a reset circuit of a data path using a clock enable signal, a reset method and a semiconductor memory device having the reset circuit. The reset circuit includes an external voltage detector and a second reset signal generator, in which the second reset signal is used to reset a block related to a data path of the semiconductor memory device. The external voltage detector detects the level of an external voltage and generates a first reset signal. The second reset signal generator performs a logical sum of an external signal, which is externally input, and the first reset signal, and generates a second reset signal. The first reset signal is used to reset blocks other than the blocks related to the data path. The external signal is a clock enable signal. In the soft reset, the blocks related to the data path are reset using the external signal which is applied at a certain level. Thus, data conflicts or ineffective data can be prevented in executing operations according to the read/write commands which are applied after the soft reset.
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申请公布号 |
US2004090830(A1) |
申请公布日期 |
2004.05.13 |
申请号 |
US20030624783 |
申请日期 |
2003.07.22 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE JUNG-BAE;JUNG WON-CHANG |
分类号 |
G11C11/407;G11C7/00;G11C7/10;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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