| 摘要 |
<p>A receiving apparatus (5000) has a common circuit (2) and three demodulator circuits (3A,3B,3C). The demodulator circuit (3A) has a second synchronization circuit (DLL) (30), a clock selecting circuit (SEL)(25), a sampling register (Sampler) (28), an alignment calculating circuit (Caliculator)(40), a decoding circuit (Decoder)(50), and a local buffer (BUF). The DLL (30) has a phase detector (PD), a LPF (32) and a voltage controlled delay circuit (VCD) (33). The other demodulator circuits (3B,3C) share the arrangement of the PD (31) and LPF (32) in the DLL (30) of the demodulator circuit (3A). This eliminates a necessity of providing the PD (31) and LPF (32) in the DLLs (30a) of the demodulator circuits (3B,3C) and hence reduces the circuit area.</p> |
