发明名称 |
Twin NAND device structure, array operations and fabrication method |
摘要 |
A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.
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申请公布号 |
US2004092066(A1) |
申请公布日期 |
2004.05.13 |
申请号 |
US20030697520 |
申请日期 |
2003.10.30 |
申请人 |
HALO LSI, INC. |
发明人 |
OGURA SEIKI;OGURA TOMOKO;SAITO TOMOYA;SATOH KIMIHIRO |
分类号 |
H01L21/8247;G11C11/56;G11C16/04;H01L21/8246;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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