| 摘要 |
A clock pulse generator includes an input terminal, an input bias setting circuit, a threshold addition circuit, a threshold subtraction circuit and a pulse combining circuit. The input bias setting circuit adds a predetermined bias voltage to the sinusoidal signal delivered from the input terminal so as to generate an addition sinusoidal signal. The threshold voltage addition circuit shapes the addition sinusoidal signal in addition to a first threshold voltage so as to generate a first pulse signal. The threshold voltage subtraction circuit shapes the addition sinusoidal signal in subtraction to a second threshold voltage so as to generate a second pulse signal. The pulse combining circuit synchronizes either one of rising or falling edges of the first clock pulse with those of the second clock pulse so as to generate an output clock pulse.
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