| 摘要 |
A memory cell array includes the ferroelectric memory cells arranged in the form of m rowsxn columns, bit lines provided along a row direction, and word lines and plate lines provided along a column direction. The word lines are provided side by side so as to intersect each other at the border between fourth row and fifth row. The arrangement allows connecting four ferroelectric memory cells to the same plate line and the same word line. Since the number of ferroelectric memory cells to be accessed simultaneously will be one-half of the number of memory cells provided in one row, unnecessary access to the ferroelectric memory cells can be reduced, thereby deterioration of the ferroelectric memory cells can be suppressed.
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