STRUCTURE AND METHOD FOR IMPROVED VERTICAL MOSFET DRAM CELL-TO-CELL ISOLATION, FOR ESPECIALLY BACK-TO-BACK MOSFET DRAM

摘要

PURPOSE: A structure and a method for improving a vertical MOSFET(Metal Oxide Semiconductor Field Effect Transistor) DRAM(Dynamic RAM) cell-to-cell isolation is provided to make a substrate more resistive to interactions between cells. CONSTITUTION: A planar semiconductor substrate includes a plurality of deep trenches having vertical FET devices(ML,MR) and a plurality of capacitors(CL,CR). Each of the FET devices and the plurality of capacitors is each located in a separate trench. The trench that is formed in a doped region in the semiconductor substrate. A planar semiconductor substrate includes a plurality of deep trenches, vertical FET devices and a plurality of capacitors each located in a separate trench. A bilateral outdiffusion strap region is formed extending into the doped region. Adjacent deep trenches have confronting pairs of outdiffusion regions extending from adjacent deep trenches into the doped region. As isolation diffusion region is formed in the doped region between back-to-back cells separating confronting outdiffusion strap regions.