| 摘要 |
PURPOSE: A method for fabricating a semiconductor device with a low resistance gate electrode is provided to improve a CCST(constant current stress test) characteristic while using the low resistance gate electrode by effectively controlling the fluorine diffused from an upper tungsten silicide layer by a process for maximizing the grain size of a crystalline silicon layer and by improving an interfacial characteristic between a gate oxide layer and the crystalline silicon layer. CONSTITUTION: A unit transistor region is formed in a predetermined region of a semiconductor substrate(20). The gate oxide layer(22) is formed on a selected region of the unit transistor region. A gate electrode is formed on the gate oxide layer, in which a crystalline silicon layer(23a) with a single grain including at least the unit transistor region and a tungsten silicide layer with plenty of tungsten are sequentially stacked. A hard mask is formed on the gate electrode. A nitrogen accumulating layer(24) is formed on the interface between the crystalline silicon layer and the gate oxide layer.
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