发明名称 |
Semiconductor isolation material deposition system and method |
摘要 |
A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.
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申请公布号 |
US6734080(B1) |
申请公布日期 |
2004.05.11 |
申请号 |
US20020159078 |
申请日期 |
2002.05.31 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
YANG NIAN;WANG JOHN JIANSHI;YANG TIEN-CHUN |
分类号 |
H01L21/762;(IPC1-7):H01L21/76 |
主分类号 |
H01L21/762 |
代理机构 |
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地址 |
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