发明名称 |
Vertical transistor DRAM structure and its manufacturing methods |
摘要 |
A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.
|
申请公布号 |
US6734484(B2) |
申请公布日期 |
2004.05.11 |
申请号 |
US20020227438 |
申请日期 |
2002.08.26 |
申请人 |
INTELLIGNET SOURCES DEVELOPMENT CORP. |
发明人 |
WU CHING-YUAN |
分类号 |
H01L21/8242;H01L27/108;H01L29/94;(IPC1-7):H01L31/116 |
主分类号 |
H01L21/8242 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|