Semiconductor memory having access transistors formed in a single well and driver transistors formed in wells different from the single well

摘要

A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N<+>-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N<+>-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.