发明名称 |
Method of maintaining data coherency in late-select synchronous pipeline type semiconductor memory device and data coherency maintaining circuit therefor |
摘要 |
A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.
|
申请公布号 |
US6735674(B2) |
申请公布日期 |
2004.05.11 |
申请号 |
US20010886308 |
申请日期 |
2001.06.21 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE KWANG-JIN |
分类号 |
G06F12/08;G06F13/16;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|