| 摘要 |
A carry skip adder has a plurality of ripple adders, in which at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C2+F*C1 is included, in which the C1 denotes a carry signal from the one group to the one upper group, and the F denotes a signal indicating whether or not outputs of all adders in the one upper group are 1s, and the C2 denotes a carry signal associated with the most upper ripple adder in the one upper group. In a group including two or more ripple adders, a plurality of ripple adders in the group are organized into a plurality of sub-groups, and a carry signal is transferred from one sub-group to one upper sub-group, a circuit for calculating C5=C4+F1*C3 is included, in which C3 denotes a carry signal from one sub-group to the one upper sub-group, and F1 denotes a signal indicating whether or not outputs of all adders in the one upper sub-group are 1s, and C4 denotes a carry signal associated with the most upper ripple adder in the one upper sub-group.
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