发明名称 |
A FREQUENCY/PHASE COMPARISON CIRCUIT WITH GATED REFERENCE AND SIGNAL INPUTS |
摘要 |
Disclosed is a frequency-locked loop (FLL), which attempts to bring abo ut frequency and phase synchronization between two signals over the control bandwidth of the loop: a reference signal and a voltage-controlled oscillato r (VCO) signal. For example, the FLL employs a reference signal generated by a crystal oscillator of frequency .function. REF and a VCO signal generated by the oscillations of an unquenched SRG resonator with tunable resonant frequency .function. RE S. These signals are connected to the inputs of a phase/frequency detector (PFD) whic h produces output pulses in response to the relationship between .function.REF and .function.RES. These pulses are applied to a loop filter (LF) which creates a voltage using some kind of charge-storage element. This loop filter voltage is a so-called error voltag e whose value is used to control the frequency of the resonator to bring the referen ce signal and VCO signal into phase synchrony.
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申请公布号 |
CA2290862(C) |
申请公布日期 |
2004.05.11 |
申请号 |
CA19992290862 |
申请日期 |
1999.11.25 |
申请人 |
PHILSAR ELECTRONICS INC. |
发明人 |
CLOUTIER, MARK MILES;SWAMINATHAN, ASHOK;CHERRY, JAMES ANDREW |
分类号 |
H03D13/00;H03L7/089;H03L7/099;H03L7/14;H03L7/18;H04L27/00;H04L27/02;(IPC1-7):G01R23/14;H03L7/091;H04B1/26 |
主分类号 |
H03D13/00 |
代理机构 |
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地址 |
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