| 摘要 |
PURPOSE: A clock buffer circuit of a memory device is provided to reduce the cost by implementing the SDR/DDR SDRAM compatible clock buffer circuit stably and effectively and by preventing the latch up. CONSTITUTION: A clock buffer circuit of a memory device includes a first signal generation block(23), a second signal generation block(25) and a differential amplification block(27). The first signal generation block(23) outputs a first signal through a feedback loop by turning on the NMOS transistor using a clock signal as an input. The second signal generation block(25) outputs a second signal through a feedback loop by turning on the NMOS transistor using a reference voltage as an input in the single data rate synchronous DRAM and outputs the second signal through the feedback loop by turning on the NMOS transistor with using the inversion signal of the clock signal as an input. And, the differential amplification block(27) amplifies the difference obtained by differentially inputting the first and the second signals.
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