| 摘要 |
In a Vss precharge scheme, a dummy cell including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line is arranged in complementary bit lines respectively. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row active is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charges of the same amount are injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.
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