发明名称 APPARATUS, METHOD AND SYSTEM FOR REDUCING LATENCY OF MEMORY DEVICES
摘要 According to one embodiment of the invention, a method is provided in which memory requests from a first component and a second component are received. The memory requests are issued by the first component and the second component to access one or more memory devices via a memory controller. The memory requests received from the first component'are accumulated in a first queue and the memory requests received from the second component are accumulated in a second queue, respectively. The memory requests accumulated in the first queue are sent to the memory controller for processing as a block of memory requests. The memory requests accumulated in the second queue are sent to the memory controller for processing as a block of memory requests.
申请公布号 WO2004031959(A3) 申请公布日期 2004.05.06
申请号 WO2003US30575 申请日期 2003.09.26
申请人 INTEL CORPORATION 发明人 CHAUDHARI, SUNIL;VINNAKOTA, BAPIRAJU
分类号 G06F13/16 主分类号 G06F13/16
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