发明名称 Circuit optimization for minimum path timing violations
摘要 A method is provided to optimize delay insertions for reducing timing violations. The method includes inserting a buffer between a driver and a receiver in a timing path and placing the buffer either inside or outside a bounding box that encloses the driver and the receiver. The placement of the buffer inside or outside the bounding box creates the appropriate effective loading on the buffer to generates the required minimum delay to avoid timing violations.
申请公布号 US2004088664(A1) 申请公布日期 2004.05.06
申请号 US20030627933 申请日期 2003.07.25
申请人 SEQUENCE DESIGN, INC. 发明人 SRINIVASAN ADI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
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