MEMORY SUBSYSTEM INCLUDING AN ERROR DETECTION MECHANISM FOR ADDRESS AND CONTROL SIGNALS

摘要

A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.