| 摘要 |
It is an aim to reduce an area required on a chip for interconnects which cross a spine center. The circuit has n inputs, which are disposed on one side of the spine center. An encoder is additionally provided, which is connected to the n inputs on an input side and to one end of the interconnects on an output side and which is likewise disposed on one side of the spine center. In this case, a number n of the inputs is greater than a number of the interconnects. A decoder, which is connected to the other end of the interconnects on the input side and to n outputs on the output side, is disposed on the other side of the spine center.
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