发明名称 |
Circuit for accurate memory read operations |
摘要 |
A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.
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申请公布号 |
US6731542(B1) |
申请公布日期 |
2004.05.04 |
申请号 |
US20020313444 |
申请日期 |
2002.12.05 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
LE BINH Q.;ACHTER MICHAEL;CLEVELAND LEE;PAULING CHEN |
分类号 |
G11C16/04;G11C16/26;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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