发明名称 |
Method and architecture for self-clocking digital delay locked loop |
摘要 |
An apparatus comprising a delay line and a control circuit. The delay line may be configured to generate an output signal in response to an input signal and one or more control signals. The delay line may be self-clocked. A phase of the output signal may be adjusted in response to the one or more control signals. The control circuit may be configured to generate the one or more control signals in response to the input signal and the output signal.
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申请公布号 |
US6731147(B2) |
申请公布日期 |
2004.05.04 |
申请号 |
US20010074737 |
申请日期 |
2001.10.29 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
FISCUS TIMOTHY E. |
分类号 |
H03L7/081;H03L7/087;H03L7/089;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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