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发明名称
半导体记忆体
摘要
在安排电荷陷入的记忆体胞元时,使用埋入式、长条状的源极线(13)以提供源极区域间的连结。字线(6)连同闸极电极形成于与源极线平行之上方。形成于一线路平面上方并与字线方向横切的汲极接触长条(10)连接汲极区域(4),并且彼此电导接。根据标准的CMOS逻辑技术,关于字线,源极区域和汲极区域皆以自对准方式形成。
申请公布号
TW200406774
申请公布日期
2004.05.01
申请号
TW092121237
申请日期
2003.08.01
申请人
亿恒科技股份公司
发明人
伊拉尔德 卡米恩斯基史泰恩
分类号
G11C16/04
主分类号
G11C16/04
代理机构
代理人
蔡清福
主权项
地址
德国
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