| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a parallel data output circuit for facilitating a timing design in achieving a data inversion function for reducing the number of signals inverted in the output. <P>SOLUTION: In the data inversion circuit, each P pieces of data comparison means 21, 22-(2P), majority decision means 31, 32-(3P), inverted flag generating means 41, 42-(4P) and data inversion means 51, 52-(5P) are in existence, respectively, and each of them is operated in parallel in a single cycle. Furthermore, when generating an inverted flag 40k indicating whether or not parallel data 101, 102-(10P) should be output in inverse, inverted flags 401, 402-(40P) are calculated from outputs from the generating means 41, 42-(4P) and from the generating means (4P) of the cycle that is one cycle prior to the single cycle. <P>COPYRIGHT: (C)2004,JPO</p> |
