DRAM PACKAGE FOR FORMING 1Mx16 I/O DRAM AND 2Mx8 I/O DRAM BY USING ONLY ONE PACKAGE, ADDRESS LINE THEREOF, AND METHOD FOR CHANGING WIDTHS OF ADDRESS LINE AND DATA LINE

摘要

PURPOSE: A DRAM package is provided to achieve a 1Mx16 I/O DRAM and a 2Mx 8 I/O DRAM by installing an address line and data line width control unit in a 1Mx16 I/O DRAM package. CONSTITUTION: A DRAM package includes a control signal input pin, address pins of n number, and data lines of q number. An address line and data line width control unit enables the address pins of n-1 number or enables the address pins of n number and the data pins of q/2 number according to a signal inputted into the control signal input pin. The address line and data line width control unit includes a data line controller(C1) for enabling the data pins of q/2 number or the data pines of q number and an address line controller(C2) for enabling the address lines of n-1 number or the address lines of n number.