| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the amount of data transaction and the size of hardware for synchronization capturing process, while holding synchronization capturing performance with high precision. <P>SOLUTION: In a delayed profile arithmetic unit 101, a delayed profile is calculated at intervals of 1/M (M is an integer of one or more) chip in the whole pass search area of the synchronization capture of a received signal. In a pass phase selection capturing unit 102, a phase of the maximum of correlation values in the delayed profile is calculated, a phase at a distance of 1/(2M) chip from the phase of the maximum correlation value is calculated, and a pass phase is selected from these calculated phases. <P>COPYRIGHT: (C)2004,JPO |
