发明名称 |
Latency control circuit and method of latency control |
摘要 |
The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.
|
申请公布号 |
US2004081013(A1) |
申请公布日期 |
2004.04.29 |
申请号 |
US20030727579 |
申请日期 |
2003.12.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
LEE SANG-BO;SONG HO-YOUNG |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C8/00;(IPC1-7):G01J1/40 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|