SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

A CPU core (6) writes encode effective bit in a data register (12). A bit shift/total control unit (13) writes the effective bit indicated in the address in the data into a secondary data buffer register (13a). When data accumulation in the secondary data buffer register (13a) is FULL, the data stored in the secondary data buffer register (13a) is written into a memory (10). When this processing is repeated, and the total of the transfer bit reaches the upper limit of the memory (10), the CPU core (6) transfers all the contents in the memory (10) to a main memory (3). Since the CPU core (6) can read the data of variable-length code in one access, the processing performance of the encoder can be improved. A data accelerator realizes high performance by the operation substantially opposite thereto.