Semiconductor circuit device with mitigated load on interconnection line

摘要

A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of the corresponding transistor are connected together by an intermediate interconnection line extending only in the region having the corresponding address interconnection line arranged. Accordingly, a high speed switching of address signals can be achieved.