发明名称 |
Method for producing an integrated semiconductor memory configuration |
摘要 |
A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and rear side of the substrate wafer respectively. Thus, a higher packing density of memory cells is engendered by the utilization of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to "0" or "1" can also be saved for each selection transistor in a ferroelectric memory configuration, if the two capacitor modules have a different structure in terms of layer thickness, surface area, or material.
|
申请公布号 |
US2004082117(A1) |
申请公布日期 |
2004.04.29 |
申请号 |
US20030609805 |
申请日期 |
2003.06.30 |
申请人 |
KASTNER MARCUS;MIKOLAJICK THOMAS |
发明人 |
KASTNER MARCUS;MIKOLAJICK THOMAS |
分类号 |
H01L21/8242;H01L21/8246;H01L27/06;H01L27/105;H01L27/108;H01L27/115;(IPC1-7):H01L21/00 |
主分类号 |
H01L21/8242 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|