A DIGITAL SYSTEM AND A METHOD FOR ERROR DETECTION THEREOF

摘要

The invention relates to a digital system (1) and the method for error detection thereof. The digital system (1) comprises, as it's main core, a Module under Test (110) included in a Digital Processing Unit (100) and a State Parity Generator (SPG) (300). The SPG (300) is an equivalent with respect to parity of the Module under Test (300). An equivalent with respect to parity is a combinatorial circuit that, when an imput vector is applied at the imput of both Module under Test (110) and SPG (300), the output of the SPG (300) generates at it's output the parity of the transfer function of the Module under Test (110). The SPG (300) generates also a warning signal W when an unused combination of the imput vector is detected, the warning signal being treated as the parity signal.