发明名称 |
Novel dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
摘要 |
A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
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申请公布号 |
US2004082125(A1) |
申请公布日期 |
2004.04.29 |
申请号 |
US20030679768 |
申请日期 |
2003.10.06 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
HOU TOU-HUNG;WANG MING-FANG;CHEN CHI-CHUN;YANG CHIH-WEI;YAO LIANG-GI;CHEN SHIH-CHANG |
分类号 |
H01L21/8234;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8234 |
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