发明名称 |
Method and apparatus for distortion analysis in nonlinear circuits |
摘要 |
A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.
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申请公布号 |
US2004083437(A1) |
申请公布日期 |
2004.04.29 |
申请号 |
US20030657304 |
申请日期 |
2003.09.08 |
申请人 |
GULLAPALLI KIRAN K.;GOURARY MARK M.;RUSAKOV SERGEI G.;ULYANOV SERGEI L.;ZHAROV MIKHAIL M. |
发明人 |
GULLAPALLI KIRAN K.;GOURARY MARK M.;RUSAKOV SERGEI G.;ULYANOV SERGEI L.;ZHAROV MIKHAIL M. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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