发明名称 Method of making a microelectronic package including a component having conductive elements on a top side and a bottom side thereof
摘要 A microelectronic element is formed from a structure including metal layers on top and bottom sides of a dielectric. Apertures are formed in the top metal layer, and vias are formed in the dielectric in alignment with the apertures. Top and bottom conductive features are formed in proximity to the vias, as by selectively depositing a metal on the metal layers or selectively etching the metal layers. The top and bottom conductive features are connected to one another by depositing a conductive material into the vias, most preferably without seeding the vias as, for example, by depositing solder in the vias.
申请公布号 US2004078963(A1) 申请公布日期 2004.04.29
申请号 US20030728306 申请日期 2003.12.04
申请人 TESSERA, INC. 发明人 JAMIL OWAIS
分类号 H01L21/48;H05K3/06;H05K3/10;H05K3/24;H05K3/40;(IPC1-7):H01L23/48;H01L23/52;H01L29/40;H05K3/00 主分类号 H01L21/48
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