| 摘要 |
A disparity signal and a 6-bit subblock are provided to a 5B/6B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 5B/6B decoding part. The disparity signal and a 4-bit subblock are provided to a 3B/4B decoding part, and a decoded data, a disparity signal, and an error candidate signal are outputted from the 3B/4B decoding part. A data hold circuit delays the disparity signal by one clock and then provides the resulting signal to the 5B/6B decoding part. At least part of the decoding processing in the 3B/4B decoding part is executed in parallel with the obtaining of the disparity signal in the 5B/6B decoding part.
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