Synchronous semiconductor memory device having dynamic memory cells and operating method thereof

摘要

A command decoder decodes the commands in synchronism with an external clock signal. The decoder sets the write active (WRA) command, read active (RDA) command, lower address latch (LAL) command and auto-refresh (REF) command based on the combination of the logic levels of the control pins. The decoder sets the auto-refresh command immediately after the execution of the write active command. An independent claim is also included for a method of operating a synchronous semiconductor memory device.