| 发明名称 |
DIGITAL LINE DELAY USING A SINGLE PORT MEMORY |
| 摘要 |
An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory ("RAM") and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.
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| 申请公布号 |
KR20040034711(A) |
申请公布日期 |
2004.04.28 |
| 申请号 |
KR20047003400 |
申请日期 |
2002.09.19 |
| 申请人 |
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发明人 |
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| 分类号 |
H04L13/08;H04N7/12;H04N5/04;H04N5/14;H04N5/77;H04N5/775;H04N5/781;H04N5/85;H04N5/907;H04N9/804 |
主分类号 |
H04L13/08 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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