| 摘要 |
PURPOSE: A method for forming a gate of a semiconductor device is provided to be capable of securing process margin using a double mask layer and preventing process failure in carrying out a depositing, etching, or CMP(Chemical Mechanical Polishing) process on an interlayer dielectric. CONSTITUTION: A polysilicon layer and the first mask layer are sequentially formed on a semiconductor substrate(5). A gate(100) and the first mask pattern(200) are formed by performing an etching process on the resultant structure. An interlayer dielectric(300) is formed on the entire surface of the resultant structure. The interlayer dielectric is partially etched by using the first mask pattern as an etch stop layer. The second mask layer(500) is formed on the etched portion of the interlayer dielectric. A contact hole is formed by selectively removing the interlayer dielectric and the second mask layer.
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