| 摘要 |
A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.
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