| 发明名称 |
DRAM having offset vertical transistors and method |
| 摘要 |
The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.
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| 申请公布号 |
US6727141(B1) |
申请公布日期 |
2004.04.27 |
| 申请号 |
US20030342419 |
申请日期 |
2003.01.14 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRONNER GARY B.;DIVAKARUNI RAMACHANDRA;KIM BYEONG;MANDELMAN JACK A. |
| 分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
| 代理机构 |
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代理人 |
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| 主权项 |
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