Hybrid data I/O for memory applications

摘要

Some forms of memory data I/O requires a parallel interface with the memory array and a serial interface with external data ports to the memory. A hybrid decoder/scan register data I/O scheme is described that offers a high speed data access to selected points along a set of scan registers that connect to the columns (bit lines) of a memory array. The interface to the memory array is a long register which comprises a chain of scan register blocks. Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches controlled by a decoder circuit to the input (or output) port of one of the scan register blocks. This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.