发明名称 Arrangement for reducing layer 3 header data supplied to switching logic on a network switch
摘要 A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a port filter configured for obtaining and filtering relevant layer 2 and layer 3 information from a received layer 2 frame. Each port filter, upon filtering the relevant layer 2 and layer 3 information from a received layer 2 frame, outputs the relevant layer 2 and layer 3 information to switching logic, enabling the switching logic to perform layer 3 processing to determine a layer 3 switching operation to be performed on the received layer 2 frame. Hence, the switching logic performs the layer 3 processing based on the relevant layer 2 and layer 3 information, without the necessity of parsing the received layer 2 and layer 3 information by the switching logic.
申请公布号 US6728246(B1) 申请公布日期 2004.04.27
申请号 US20000502570 申请日期 2000.02.11
申请人 ADVANCED MICRO DEVICES, INC. 发明人 EGBERT CHANDAN;KANURI MRUDULA
分类号 H04J3/16;H04L12/28;H04L12/56;(IPC1-7):H04L12/28 主分类号 H04J3/16
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