Multiple access parallel memory and method

摘要

A memory architecture for multiple inputs comprises a common memory structure having a plurality of data locations for storing data units and an input section for providing a plurality of input ports with access to the common memory structure. The input section includes a memory buffer for each input port which can store a number of data units equal to the number of input ports, and a bus allowing each memory buffer to write a plurality of data units across the memory structure at least once during a memory-access cycle. The common memory structure includes a number of memory banks equal to the number of input ports. This structure enables the memory banks to be implemented as low speed devices. The memory architecture is suitable for use in ATM system components.