发明名称 Lower-jitter phase-locked loop
摘要 A circuit combines the outputs of two or more phase locked loops to reduce jitter to a level below that of an individual phase locked loop. A digital version of the circuit uses a majority function to determine the median value of the phase locked loops. An analog version of the circuit averages the outputs of the phase locked loops.
申请公布号 US6728327(B1) 申请公布日期 2004.04.27
申请号 US20000477658 申请日期 2000.01.05
申请人 LSI LOGIC CORPORATION 发明人 SCHONER BRIAN
分类号 H03B1/04;H03B21/02;H03L7/07;(IPC1-7):H03D3/24;H03K3/17 主分类号 H03B1/04
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