发明名称 |
Method and apparatus for simulated error injection for processor deconfiguration design verification |
摘要 |
A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.
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申请公布号 |
US6728668(B1) |
申请公布日期 |
2004.04.27 |
申请号 |
US19990434876 |
申请日期 |
1999.11.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KITAMORN ALONGKRON;MCLAUGHLIN CHARLES ANDREW;NGUYEN CAMVAN THI;PATEL JAYESHKUMAR M. |
分类号 |
G06F9/44;(IPC1-7):G06F9/44 |
主分类号 |
G06F9/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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