| 摘要 |
<P>PROBLEM TO BE SOLVED: To surely detect a PLL drift warning in a drift state in which a subordinate clock is caused to flow to a reference clock and even while the reference clock and the subordinate clock are locked by a phase outside a regulated range. <P>SOLUTION: While step-out occurs due to a PLL failure or the like to cause the subordinate clock to flow, the step-out is detected by monitoring the continuity of a phase relation because the phase relation between the reference clock and the subordinate clock repeats normality/abnormality. The phase relation between the reference clock and the subordinate clock is monitored at the same time, and if synchronization (lock) is performed in the phase outside the regulated range, the step-out is detected. A drift warning detecting part 31C determines drift abnormality on the basis of those information. <P>COPYRIGHT: (C)2004,JPO |
