SUBLITHOGRAPHIC NANOSCALE MEMORY ARCHITECTURE

摘要

A memory array comprising nanoscale wires is disclosed. The nanoscale wiresare addressed by means of controllable regions axially and/or radiallydistributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires andmicroscale wires. In a two-dimensional emobdiment, memory locations aredefined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing pointsbetween nanoscale wires located in different vertical layers.