| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent the deterioration of processing capability due to a low frequency even when the frequency of a synchronizing clock signal is variable, and to suppress power consumption. <P>SOLUTION: For example, when a selector part 31-2 receives a selection command selectB set corresponding to the frequency of a synchronizing clock signal CLK, indicating that a storing part 12-2 is by-passed, data inputted and stored in a storing part 12-1 in the prescribed first clock of the synchronizing clock signal CLK are transmitted through a selector part 31-1 and a signal processing part 13-1 in the next second clock, and by-passed through the storing 12-2, and transmitted through a selector part 31-2 as they are, and further transmitted through a signal processing part 13-2, and inputted and stored in a storing part 12-3. This invention may be applied to a data processor such as a CPU, DSP and a filter or a bus. <P>COPYRIGHT: (C)2004,JPO |
