| 摘要 |
Methods and systems for protecting integrated circuits from power on sequence currents, including methods and systems for biasing transistors in paths susceptible to power-on sequence damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on. In an embodiment, the invention is applied to a circuit having first and second terminals (114, 118) coupled to first and second power supplies (110, 112), respectively. The invention protects the circuit in the event that the first power supply is powered-on before the second supply. |
